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Register a new userIntrinsic synaptic plasticity of ferroelectric field effect transistors for online learning
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Added by
Abhronil Sengupta
Publication date
2021
fields
Informatics Engineering
and research's language is
English
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Nanoelectronic devices emulating neuro-synaptic functionalities through their intrinsic physics at low operating energies is imperative toward the realization of brain-like neuromorphic computers. In this work, we leverage the non-linear voltage dependent partial polarization switching of a ferroelectric field effect transistor to mimic plasticity characteristics of biological synapses. We provide experimental measurements of the synaptic characteristics for a $28nm$ high-k metal gate technology based device and develop an experimentally calibrated device model for large-scale system performance prediction. Decoupled read-write paths, ultra-low programming energies and the possibility of arranging such devices in a cross-point architecture demonstrate the synaptic efficacy of the device. Our hardware-algorithm co-design analysis reveals that the intrinsic plasticity of the ferroelectric devices has potential to enable unsupervised local learning in edge devices with limited training data.
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Homeostatic plasticity is a stabilizing mechanism that allows neural systems to maintain their activity around a functional operating point. This is an extremely useful mechanism for neuromorphic computing systems, as it can be used to compensate for chronic shifts, for example due to changes in the network structure. However, it is important that this plasticity mechanism operates on time scales that are much longer than conventional synaptic plasticity ones, in order to not interfere with the learning process. In this paper we present a novel ultra-low leakage cell and an automatic gain control scheme that can adapt the gain of analog log-domain synapse circuits over extremely long time scales. To validate the proposed scheme, we implemented the ultra-low leakage cell in a standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) process, and integrated it in an array of dynamic synapses connected to an adaptive integrate and fire neuron. We describe the circuit and demonstrate how it can be configured to scale the gain of all synapses afferent to the silicon neuron in a way to keep the neurons average firing rate constant around a set operating point. The circuit occupies a silicon area of 84 {mu}m x 22 {mu}m and consumes approximately 10.8 nW with a 1.8 V supply voltage. It exhibits time constants of up to 25 kilo-seconds, thanks to a controllable leakage current that can be scaled down to 1.2 atto-Amps (7.5 electrons/s).
Negative capacitance (NC) in ferroelectrics, which stems from the imperfect screening of polarization, is considered a viable approach to lower voltage operation in the field-effect transistors (FETs) used in logic switches. In this paper, we discuss the implications of the transient nature of negative capacitance for its practical application. It is suggested that the NC effect needs to be characterized at the proper time scale to identify the type of circuits where functional NC-FETs can be used effectively.
Homeostatic plasticity is a stabilizing mechanism commonly observed in real neural systems that allows neurons to maintain their activity around a functional operating point. This phenomenon can be used in neuromorphic systems to compensate for slowly changing conditions or chronic shifts in the system configuration. However, to avoid interference with other adaptation or learning processes active in the neuromorphic system, it is important that the homeostatic plasticity mechanism operates on time scales that are much longer than conventional synaptic plasticity ones. In this paper we present an ultra-low leakage circuit, integrated into an automatic gain control scheme, that can implement the synaptic scaling homeostatic process over extremely long time scales. Synaptic scaling consists in globally scaling the synaptic weights of all synapses impinging onto a neuron maintaining their relative differences, to preserve the effects of learning. The scheme we propose controls the global gain of analog log-domain synapse circuits to keep the neurons average firing rate constant around a set operating point, over extremely long time scales. To validate the proposed scheme, we implemented the ultra-low leakage synaptic scaling homeostatic plasticity circuit in a standard 0.18 $mu$m Complementary Metal-Oxide Semiconductor (CMOS) process, and integrated it in an array of dynamic synapses connected to an adaptive integrate and fire neuron. The circuit occupies a silicon area of 84 $mu$m x 22 $mu$m and consumes approximately 10.8 nW with a 1.8 V supply voltage. We present experimental results from the homeostatic circuit and demonstrate how it can be configured to exhibit time scales of up to 100 kilo-seconds, thanks to a controllable leakage current that can be scaled down to 0.45 atto-Amperes (2.8 electrons/s).
Synaptic plasticity is the capacity of a preexisting connection between two neurons to change in strength as a function of neural activity. Because synaptic plasticity is the major candidate mechanism for learning and memory, the elucidation of its constituting mechanisms is of crucial importance in many aspects of normal and pathological brain function. In particular, a prominent aspect that remains debated is how the plasticity mechanisms, that encompass a broad spectrum of temporal and spatial scales, come to play together in a concerted fashion. Here we review and discuss evidence that pinpoints to a possible non-neuronal, glial candidate for such orchestration: the regulation of synaptic plasticity by astrocytes.
We report the fabrication of back-gated field-effect transistors (FETs) using ultra-thin, mechanically exfoliated MoSe2 flakes. The MoSe2 FETs are n-type and possess a high gate modulation, with On/Off ratios larger than 106. The devices show asymmetric characteristics upon swapping the source and drain, a finding explained by the presence of Schottky barriers at the metal contact/MoSe2 interface. Using four-point, back-gated devices we measure the intrinsic conductivity and mobility of MoSe2 as a function of gate bias, and temperature. Samples with a room temperature mobility of ~50 cm2/V.s show a strong temperature dependence, suggesting phonons are a dominant scattering mechanism.
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