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Register a new userThe Critical Role of Charge Balance on the Memory Characteristics of Ferroelectric Field-Effect Transistors
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Ferroelectric field-effect transistors (Fe-FETs) with ferroelectric hafnium oxide (FE HfO2) as gate insulator are being extensively explored as a promising device candidate for three-dimensional (3D) NAND memory application. FE HfO2 exhibits long retention over 10 years, high endurance over 1012 cycles, high speed with sub-ns polarization switching, and high remnant polarization of 10-30 {mu}C/cm2. However, the performance of Fe-FETs is known to be much worse than FE HfO2 capacitors, which is not completely understood. In this work, we developed a comprehensive Fe-FET model based on a charge balance framework. The role of charge balance and the impact of leakage-assist-switching mechanism on the memory characteristics of Fe-FETs with M/FE/DE/S (Metal/Ferroelectric/Dielectric/Semiconductor) gate stack is studied. It is found that the FE/DE interface and DE layer instead of FE layer is critical to determine the memory characteristics of Fe-FETs, and experimental Fe-FETs can be well explained by this model, where the discrepancy between FE capacitors and Fe-FETs are successfully understood.
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Magnetic skyrmions are of considerable interest for low-power memory and logic devices because of high speed at low current and high stability due to topological protection. We propose a skyrmion field-effect transistor based on a gate-controlled Dzyaloshinskii-Moriya interaction. A key working principle of the proposed skyrmion field-effect transistor is a large transverse motion of skyrmion, caused by an effective equilibrium damping-like spin-orbit torque due to spatially inhomogeneous Dzyaloshinskii-Moriya interaction. This large transverse motion can be categorized as the skyrmion Hall effect, but has been unrecognized previously. The propose device is capable of multi-bit operation and Boolean functions, and thus is expected to serve as a low-power logic device based on the magnetic solitons.
At the LaAlO$_3$-SrTiO$_3$ interface, electronic phase transitions can be triggered by modulation of the charge carrier density, making this system an excellent prospect for the realization of versatile electronic devices. Here, we report repeatable transistor operation in locally gated LaAlO$_3$-SrTiO$_3$ field-effect devices of which the LaAlO$_3$ dielectric is only four unit cells thin, the critical thickness for conduction at this interface. This extremely thin dielectric allows a very efficient charge modulation of ${sim}3.2times10^{13}$ cm$^{-2}$ within a gate-voltage window of $pm1$ V, as extracted from capacitance-voltage measurements. These also reveal a large stray capacitance between gate and source, presenting a complication for nanoscale device operation. Despite the small LaAlO$_3$ thickness, we observe a negligible gate leakage current, which we ascribe to the extension of the conducting states into the SrTiO$_3$ substrate.
The application of imaging techniques based on ensembles of nitrogen-vacancy (NV) sensors in diamond to characterise electrical devices has been proposed, but the compatibility of NV sensing with operational gated devices remains largely unexplored. Here we fabricate graphene field-effect transistors (GFETs) directly on the diamond surface and characterise them via NV microscopy. The current density within the gated graphene is reconstructed from NV magnetometry under both mostly p- and n-type doping, but the exact doping level is found to be affected by the measurements. Additionally, we observe a surprisingly large modulation of the electric field at the diamond surface under an applied gate potential, seen in NV photoluminescence and NV electrometry measurements, suggesting a complex electrostatic response of the oxide-graphene-diamond structure. Possible solutions to mitigate these effects are discussed.
Transient currents in atomically thin MoTe$_2$ field-effect transistor are measured during cycles of pulses through the gate electrode. The transients are analyzed in light of a newly proposed model for charge trapping dynamics that renders a time-dependent change in threshold voltage the dominant effect on the channel hysteretic behavior over emission currents from the charge traps. The proposed model is expected to be instrumental in understanding the fundamental physics that governs the performance of atomically thin FETs and is applicable to the entire class of atomically thin-based devices. Hence, the model is vital to the intelligent design of fast and highly efficient opto-electronic devices.
In recent years, resistive RAM often referred to as memristor is actively pursued as a replacement for nonvolatile-flash memory due to its superior characteristics such as high density, scalability, low power operation, high endurance, and fast operating speed. However, one of the challenges that need to be overcome is the loss of retention for both ON- and OFF-states; the retention loss. While various models are proposed to explain the retention loss in memristors consisting of a switching layer, in this paper, we propose that the nucleation of clusters made of electrical charges, charge-clusters, in the switching layer acts as a potential root cause for the retention loss. The nucleation results from localized electric-field produced intermittently during cyclic switching operations. We use the phase-field method to illustrate how the nucleation of charge-clusters gives rise to the retention loss. Our results suggest that the degree at which the retention loss arises is linked to the number of cyclic switching operations since the probability at which nucleation centers form increases with the number of cycle switching operations, which is consistent with a range of experimental findings previously reported.
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