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Register a new userCMOS-based cryogenic control of silicon quantum circuits
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The most promising quantum algorithms require quantum processors hosting millions of quantum bits when targeting practical applications. A major challenge towards large-scale quantum computation is the interconnect complexity. In current solid-state qubit implementations, a major bottleneck appears between the quantum chip in a dilution refrigerator and the room temperature electronics. Advanced lithography supports the fabrication of both CMOS control electronics and qubits in silicon. When the electronics are designed to operate at cryogenic temperatures, it can ultimately be integrated with the qubits on the same die or package, overcoming the wiring bottleneck. Here we report a cryogenic CMOS control chip operating at 3K, which outputs tailored microwave bursts to drive silicon quantum bits cooled to 20mK. We first benchmark the control chip and find electrical performance consistent with 99.99% fidelity qubit operations, assuming ideal qubits. Next, we use it to coherently control actual silicon spin qubits and find that the cryogenic control chip achieves the same fidelity as commercial instruments. Furthermore, we highlight the extensive capabilities of the control chip by programming a number of benchmarking protocols as well as the Deutsch-Josza algorithm on a two-qubit quantum processor. These results open up the path towards a fully integrated, scalable silicon-based quantum computer.
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Complementary metal-oxide semiconductor (CMOS) technology has radically reshaped the world by taking humanity to the digital age. Cramming more transistors into the same physical space has enabled an exponential increase in computational performance, a strategy that has been recently hampered by the increasing complexity and cost of miniaturization. To continue achieving significant gains in computing performance, new computing paradigms, such as quantum computing, must be developed. However, finding the optimal physical system to process quantum information, and scale it up to the large number of qubits necessary to build a general-purpose quantum computer, remains a significant challenge. Recent breakthroughs in nanodevice engineering have shown that qubits can now be manufactured in a similar fashion to silicon field-effect transistors, opening an opportunity to leverage the know-how of the CMOS industry to address the scaling challenge. In this article, we focus on the analysis of the scaling prospects of quantum computing systems based on CMOS technology.
Superconducting quantum circuits are typically housed in conducting enclosures in order to control their electromagnetic environment. As devices grow in physical size, the electromagnetic modes of the enclosure come down in frequency and can introduce unwanted long-range cross-talk between distant elements of the enclosed circuit. Incorporating arrays of inductive shunts such as through-substrate vias or machined pillars can suppress these effects by raising these mode frequencies. Here, we derive simple, accurate models for the modes of enclosures that incorporate such inductive-shunt arrays. We use these models to predict that cavity-mediated inter-qubit couplings and drive-line cross-talk are exponentially suppressed with distance for arbitrarily large quantum circuits housed in such enclosures, indicating the promise of this approach for quantum computing. We find good agreement with a finite-element simulation of an example device containing more than 400 qubits.
Nuclear spins in the solid state are both a cause of decoherence and a valuable resource for spin qubits. In this work, we demonstrate control of isolated 29Si nuclear spins in silicon carbide (SiC) to create an entangled state between an optically active divacancy spin and a strongly coupled nuclear register. We then show how isotopic engineering of SiC unlocks control of single weakly coupled nuclear spins and present an ab initio method to predict the optimal isotopic fraction which maximizes the number of usable nuclear memories. We bolster these results by reporting high-fidelity electron spin control (F=99.984(1)%), alongside extended coherence times (T2=2.3 ms, T2DD>14.5 ms), and a >40 fold increase in dephasing time (T2*) from isotopic purification. Overall, this work underlines the importance of controlling the nuclear environment in solid-state systems and provides milestone demonstrations that link single photon emitters with nuclear memories in an industrially scalable material.
Generating entangled graph states of qubits requires high entanglement rates, with efficient detection of multiple indistinguishable photons from separate qubits. Integrating defect-based qubits into photonic devices results in an enhanced photon collection efficiency, however, typically at the cost of a reduced defect emission energy homogeneity. Here, we demonstrate that the reduction in defect homogeneity in an integrated device can be partially offset by electric field tuning. Using photonic device-coupled implanted nitrogen vacancy (NV) centers in a GaP-on-diamond platform, we demonstrate large field-dependent tuning ranges and partial stabilization of defect emission energies. These results address some of the challenges of chip-scale entanglement generation.
Phosphorus donor spins in silicon offer a number of promising characteristics for the implementation of robust qubits. Amongst various concepts for scale-up, the shared-control concept takes advantage of 3D scanning tunnelling microscope (STM) fabrication techniques to minimise the number of control lines, allowing the donors to be placed at the pitch limit of $geq$30 nm, enabling dipole interactions. A fundamental challenge is to exploit the faster exchange interaction, however, the donor spacings required are typically 15 nm or less, and the exchange interaction is notoriously sensitive to lattice site variations in donor placement. This work presents a proposal for a fast exchange-based surface-code quantum computer architecture which explicitly addresses both donor placement imprecision commensurate with the atomic-precision fabrication techniques and the stringent qubit pitch requirements. The effective pitch is extended by incorporation of an intermediate donor acting as an exchange-interaction switch. We consider both global control schemes and a scheduled series of operations by designing GRAPE pulses for individual CNOTs based on coupling scenarios predicted by atomistic tight-binding simulations. The architecture is compatible with the existing fabrication capabilities and may serve as a blueprint for the experimental implementation of a full-scale fault-tolerant quantum computer based on donor impurities in silicon.
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