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Register a new userOver 1% magnetoresistance ratio at room temperature in non-degenerate silicon-based lateral spin valves
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H. Koike
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To augment the magnetoresistance (MR) ratio of n-type non-degenerate Si-based lateral spin valves (Si-LSVs), we modify the doping profile in the Si layer and introduce a larger local strain into the Si channel by changing a capping insulator. The highest MR ratio of 1.4% is achieved in the Si-LSVs through these improvements, with significant roles played by a reduction in the resistance-area product of the ferromagnetic contacts and an enhancement of the momentum relaxation time in the Si channel.
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Room temperature operation of a spin exclusive or (XOR) gate was demonstrated in lateral spin valve devices with nondegenerate silicon (Si) channels. The spin XOR gate is a fundamental part of the magnetic logic gate (MLG) that enables reconfigurable and nonvolatile NAND or OR operation in one device. The device for the spin XOR gate consists of three iron (Fe)/cobalt (Co)/magnesium oxide (MgO) electrodes, i.e., two input and one output electrodes. Spins are injected into the Si channel from the input electrodes whose spin angular momentum corresponds to the binary input 1 or 0. The spin drift effect is controlled by a lateral electric field in the Si channel to adjust the spin accumulation voltages under two different parallel configurations, corresponding to (1, 1) and (0, 0), so that they exhibit the same value. As a result, the spin accumulation voltage detected by the output electrode exhibits three different voltages, represented by an XOR gate. The one-dimensional spin drift-diffusion model clearly explains the obtained XOR behavior. Charge current detection of the spin XOR gate is also demonstrated. The detected charge current has a maximum of 0.94 nA, the highest value in spin XOR gates reported thus far. Furthermore, gate voltage modulation of the spin XOR gate is also demonstrated, which enables operation of multiple MLG devices.
The temperature evolution of spin relaxation time, {tau}sf, in degenerate silicon (Si)-based lateral spin valves is investigated by means of the Hanle effect measurements. {tau}sf at 300 K is estimated to be 1.68+-0.03 ns and monotonically increased with decreasing temperature down to 100 K. Below 100 K, in contrast, it shows almost a constant value of ca. 5 ns. The temperature dependence of the conductivity of the Si channel shows a similar behavior to that of the {tau}sf, i.e., monotonically increasing with decreasing temperature down to 100 K and a weak temperature dependence below 100 K. The temperature evolution of conductivity reveals that electron scattering due to magnetic impurities is negligible. A comparison between {tau}sf and momentum scattering time reveals that the dominant spin scattering mechanism in the Si is the Elliott-Yafet mechanism, and the ratio of the momentum scattering time to the {tau}sf attributed to nonmagnetic impurities is approximately 3.77*10^-6, which is more than two orders of magnitude smaller than that of copper.
We present inverted spin-valves fabricated from CVD-grown bilayer graphene (BLG) that show more than a doubling in device performance at room temperature compared to state-of-the art bilayer graphene spin-valves. This is made possible by a PDMS droplet-assisted full-dry transfer technique that compensates for previous process drawbacks in device fabrication. Gate-dependent Hanle measurements show spin lifetimes of up to 5.8 ns and a spin diffusion length of up to 26 $mu$m at room temperature combined with a charge carrier mobility of $approx$ 24 000 cm$^{2}$(Vs)$^{-1}$ for the best device. Our results demonstrate that CVD-grown BLG shows equally good room temperature spin transport properties as both CVD-graphene and even exfoliated single-layer graphene.
We demonstrate spin-accumulation signals controlled by the gate voltage in a metal-oxide-semiconductor field effect transistor structure with a Si channel and a CoFe/$n^{+}$-Si contact at room temperature. Under the application of a back-gate voltage, we clearly observe the three-terminal Hanle-effect signal, i.e., spin-accumulation signal. The magnitude of the spin-accumulation signals can be reduced with increasing the gate voltage. We consider that the gate controlled spin signals are attributed to the change in the carrier density in the Si channel beneath the CoFe/$n^{+}$-Si contact. This study is not only a technological jump for Si-based spintronic applications with gate structures but also reliable evidence for the spin injection into the semiconducting Si channel at room temperature.
Spin transport in non-degenerate semiconductors is expected to pave a way to the creation of spin transistors, spin logic devices and reconfigurable logic circuits, because room temperature (RT) spin transport in Si has already been achieved. However, RT spin transport has been limited to degenerate Si, which makes it difficult to produce spin-based signals because a gate electric field cannot be used to manipulate such signals. Here, we report the experimental demonstration of spin transport in non-degenerate Si with a spin metal-oxide-semiconductor field-effect transistor (MOSFET) structure. We successfully observed the modulation of the Hanle-type spin precession signals, which is a characteristic spin dynamics in non-degenerate semiconductor. We obtained long spin transport of more than 20 {mu}m and spin rotation, greater than 4{pi} at RT. We also observed gate-induced modulation of spin transport signals at RT. The modulation of spin diffusion length as a function of a gate voltage was successfully observed, which we attributed to the Elliott-Yafet spin relaxation mechanism. These achievements are expected to make avenues to create of practical Si-based spin MOSFETs.
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