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Register a new userFabrication process and failure analysis for robust quantum dots in silicon
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J. P. Dodson
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We present an improved fabrication process for overlapping aluminum gate quantum dot devices on Si/SiGe heterostructures that incorporates low-temperature inter-gate oxidation, thermal annealing of gate oxide, on-chip electrostatic discharge (ESD) protection, and an optimized interconnect process for thermal budget considerations. This process reduces gate-to-gate leakage, damage from ESD, dewetting of aluminum, and formation of undesired alloys in device interconnects. Additionally, cross-sectional scanning transmission electron microscopy (STEM) images elucidate gate electrode morphology in the active region as device geometry is varied. We show that overlapping aluminum gate layers homogeneously conform to the topology beneath them, independent of gate geometry, and identify critical dimensions in the gate geometry where pattern transfer becomes non-ideal, causing device failure.
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Axially-stacked quantum dots (QDs) in nanowires (NWs) have important applications in fabricating nanoscale quantum devices and lasers. Although their performances are very sensitive to crystal quality and structures, there is relatively little study on defect-free growth with Au-free mode and structure optimisation for achiving high performances. Here, we report a detailed study of the first self-catalyzed defect-free axially-stacked deep NWQDs. High structural quality is maintained when 50 GaAs QDs are placed in a single GaAsP NW. The QDs have very sharp interfaces (1.8~3.6 nm) and can be closely stacked with very similar structural properties. They exhibit the deepest carrier confinement (~90 meV) and largest exciton-biexciton splitting (~11 meV) among non-nitride III-V NWQDs, and can maintain good optical properties after being stored in ambient atmosphere for over 6 months due to excellent stability. Our study sets a solid foundation to build high-performance axially-stacked NWQD devices that are compatible with CMOS technologies.
Many promising applications of single crystal diamond and its color centers as sensor platform and in photonics require free-standing membranes with a thickness ranging from several micrometers to the few 100 nm range. In this work, we present an approach to conveniently fabricate such thin membranes with up to about one millimeter in size. We use commercially available diamond plates (thickness 50 $mu$m) in an inductively coupled reactive ion etching process which is based on argon, oxygen and SF$_6$. We thus avoid using toxic, corrosive feed gases and add an alternative to previously presented recipes involving chlorine-based etching steps. Our membranes are smooth (RMS roughness <1 nm) and show moderate thickness variation (central part: <1 $mu$m over $approx ,$200x200 $mu$m$^2$). Due to an improved etch mask geometry, our membranes stay reliably attached to the diamond plate in our chlorine-based as well as SF$_6$-based processes. Our results thus open the route towards higher reliability in diamond device fabrication and up-scaling.
Given its unrivaled potential of integration and scalability, silicon is likely to become a key platform for large-scale quantum technologies. Individual electron-encoded artificial atoms either formed by impurities or quantum dots have emerged as a promising solution for silicon-based integrated quantum circuits. However, single qubits featuring an optical interface needed for large-distance exchange of information have not yet been isolated in such a prevailing semiconductor. Here we show the isolation of single optically-active point defects in a commercial silicon-on-insulator wafer implanted with carbon atoms. These artificial atoms exhibit a bright, linearly polarized single-photon emission at telecom wavelengths suitable for long-distance propagation in optical fibers. Our results demonstrate that despite its small bandgap (~ 1.1 eV) a priori unfavorable towards such observation, silicon can accommodate point defects optically isolable at single scale, like in wide-bandgap semiconductors. This work opens numerous perspectives for silicon-based quantum technologies, from integrated quantum photonics to quantum communications and metrology.
Quantum computation relies on accurate measurements of qubits not only for reading the output of the calculation, but also to perform error correction. Most proposed scalable silicon architectures utilize Pauli blockade of triplet states for spin-to-charge conversion. In recent experiments, there have been instances when instead of conventional triplet blockade readout, Pauli blockade is sustained only between parallel spin configurations, with $|T_0rangle$ relaxing quickly to the singlet state and leaving $|T_+rangle$ and $|T_-rangle$ states blockaded -- which we call textit{parity readout}. Both types of blockade can be used for readout in quantum computing, but it is crucial to maximize the fidelity and understand in which regime the system operates. We devise and perform an experiment in which the crossover between parity and singlet-triplet readout can be identified by investigating the underlying physics of the $|T_0rangle$ relaxation rate. This rate is tunable over four orders of magnitude by controlling the Zeeman energy difference between the dots induced by spin-orbit coupling, which in turn depends on the direction of the applied magnetic field. We suggest a theoretical model incorporating charge noise and relaxation effects that explains quantitatively our results. Investigating the model both analytically and numerically, we identify strategies to obtain on-demand either singlet-triplet or parity readout consistently across large arrays of dots. We also discuss how parity readout can be used to perform full two-qubit state tomography and its impact on quantum error detection schemes in large-scale silicon quantum computers.
A two-qubit controlled-NOT (CNOT) gate, realized by a controlled-phase (C-phase) gate combined with single-qubit gates, has been experimentally implemented recently for quantum-dot spin qubits in isotopically enriched silicon, a promising solid-state system for practical quantum computation. In the experiments, the single-qubit gates have been demonstrated with fault-tolerant control-fidelity, but the infidelity of the two-qubit C-phase gate is, primarily due to the electrical noise, still higher than the required error threshold for fault-tolerant quantum computation (FTQC). Here, by taking the realistic system parameters and the experimental constraints on the control pulses into account, we construct experimentally realizable high-fidelity CNOT gates robust against electrical noise with the experimentally measured $1/f^{1.01}$ noise spectrum and also against the uncertainty in the interdot tunnel coupling amplitude. Our optimal CNOT gate has about two orders of magnitude improvement in gate infidelity over the ideal C-phase gate constructed without considering any noise effect. Furthermore, within the same control framework, high-fidelity and robust single-qubit gates can also be constructed, paving the way for large-scale FTQC.
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