No Arabic abstract
Atomic precision advanced manufacturing (APAM) offers creation of donor devices in an atomically thin layer doped beyond the solid solubility limit, enabling unique device physics. This presents an opportunity to use APAM as a pathfinding platform to investigate digital electronics at the atomic limit. Scaling to smaller transistors is increasingly difficult and expensive, necessitating the investigation of alternative fabrication paths that extend to the atomic scale. APAM donor devices can be created using a scanning tunneling microscope (STM). However, these devices are not currently compatible with industry standard fabrication processes. There exists a tradeoff between low thermal budget (LT) processes to limit dopant diffusion and high thermal budget (HT) processes to grow defect-free layers of epitaxial Si and gate oxide. To this end, we have developed an LT epitaxial Si cap and LT deposited Al2O3 gate oxide integrated with an atomically precise single-electron transistor (SET) that we use as an electrometer to characterize the quality of the gate stack. The surface-gated SET exhibits the expected Coulomb blockade behavior. However, the leverage of the gate over the SET is limited by defects in the layers above the SET, including interfaces between the Si and oxide, and structural and chemical defects in the Si cap. We propose a more sophisticated gate stack and process flow that is predicted to improve performance in future atomic precision devices.
Surface acoustic wave (SAW) devices based on thin films of ZnO are a well established technology. However, SAW devices on bulk ZnO crystals are not practical at room temperature due to the significant damping caused by finite electrical conductivity of the crystal. Here, by operating at low temperatures, we demonstrate effective SAW devices on the (0001) surface of bulk ZnO crystals, including a delay line operating at SAW wavelengths of {lambda} = 4 and 6 {mu}m and a one-port resonator at a wavelength of {lambda} = 1.6 {mu}m. We find that the SAW velocity is temperature dependent, reaching $v simeq 2.68$ km/s at 10mK. Our resonator reaches a maximum quality factor of $Q_i simeq 1.5times 10^5$, demonstrating that bulk ZnO is highly viable for low temperature SAW applications. The performance of the devices is strongly correlated with the bulk conductivity, which quenches SAW transmission above about 200 K.
THz quantum cascade lasers based on a novel buried cavity geometry are demonstrated by combining double-metal waveguides with proton implantation. Devices are realised with emission at 2.8 THz, displaying ultra low threshold currents of 19 mA at 4K in both pulsed and continuous wave operation. Thanks to the semiconductor material on both sides of the active region and to the narrow width of the top metal strip, the thermal properties of these devices have been greatly improved. A decrease of the thermal resistance by over a factor of two compared to standard ridge double-metal lasers of similar size has been measured.
We show that a scanning capacitance microscope (SCM) can image buried delta-doped donor nanostructures fabricated in Si via a recently developed atomic-precision scanning tunneling microscopy (STM) lithography technique. A critical challenge in completing atomic-precision nanoelectronic devices is to accurately align mesoscopic metal contacts to the STM defined nanostructures. Utilizing the SCMs ability to image buried dopant nanostructures, we have developed a technique by which we are able to position metal electrodes on the surface to form contacts to underlying STM fabricated donor nanostructures with a measured accuracy of 300 nm. Low temperature (T=4K) transport measurements confirm successful placement of the contacts to the donor nanostructures.
We report results of experimental investigation of the low-frequency noise in the top-gate graphene transistors. The back-gate graphene devices were modified via addition of the top gate separated by 20 nm of HfO2 from the single-layer graphene channels. The measurements revealed low flicker noise levels with the normalized noise spectral density close to 1/f (f is the frequency) and Hooge parameter below 2 x 10^-3. The analysis of the noise spectral density dependence on the top and bottom gate biases helped us to elucidate the noise sources in these devices and develop a strategy for the electronic noise reduction. The obtained results are important for all proposed graphene applications in electronics and sensors.
Complex integrated circuits require multiple wiring layers. In complementary metal-oxide-semiconductor (CMOS) processing, these layers are robustly separated by amorphous dielectrics. These dielectrics would dominate energy loss in superconducting integrated circuits. Here we demonstrate a procedure that capitalizes on the structural benefits of inter-layer dielectrics during fabrication and mitigates the added loss. We separate and support multiple wiring layers throughout fabrication using SiO$_2$ scaffolding, then remove it post-fabrication. This technique is compatible with foundry level processing and the can be generalized to make many different forms of low-loss multi-layer wiring. We use this technique to create freestanding aluminum vacuum gap crossovers (airbridges). We characterize the added capacitive loss of these airbridges by connecting ground planes over microwave frequency $lambda/4$ coplanar waveguide resonators and measuring resonator loss. We measure a low power resonator loss of $sim 3.9 times 10^{-8}$ per bridge, which is 100 times lower than dielectric supported bridges. We further characterize these airbridges as crossovers, control line jumpers, and as part of a coupling network in gmon and fuxmon qubits. We measure qubit characteristic lifetimes ($T_1$s) in excess of 30 $mu$s in gmon devices.