Do you want to publish a course? Click here

Mismatch error correction for time interleaved analog-to-digital converter over a wide frequency range

130   0   0.0 ( 0 )
 Added by Lei Zhao
 Publication date 2018
and research's language is English




Ask ChatGPT about the research

High-speed high-resolution Analog-to-Digital Conversion is the key part for waveform digitization in physics experiments and many other domains. This paper presents a new fully digital correction of mismatch errors among the channels in Time Interleaved Analog-to-Digital Converter (TIADC) systems. We focus on correction with wide-band input signal, which means that we can correct the mismatch errors for any frequency point in a broad band with only one set of filter coefficients. Studies were also made to show how to apply the correction algorithm beyond the base band, i.e. other Nyquist zones in the under-sampling situation. Structure of the correction algorithm is presented in this paper, as well as simulation results. To evaluate the correction performance, we actually conducted a series of tests with two TIADC systems. The results indicate that the performance of both two TIADC systems can be greatly improved by correction, and the Effective Number Of Bits (ENOB) is successfully improved to be better than 9.5 bits and 5.5 bits for an input signal up to the bandwidth (-3dB) range in the 1.6-Gsps 14-bit and the 10-Gsps 8-bit TIADC systems, respectively. Tests were also conducted for input signal frequencies in the second Nyquist zone, which shows that the correction algorithms also work well as expected.



rate research

Read More

Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of off-the-shelf TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition systems and the interface to the online FARM of KLOE-2.
A high-precision charge measurement can be achieved by the area integration of a digitized quasi-Gaussian signal after the signal passes through the shaper and analog-to-digital converter (ADC). The charge measurement contains an error due to the uncertainty of the first sampled point of a signal waveform. To reduce the error, we employ a time-to-digital converter (TDC) to measure the uncertainty precisely, and we design correction algorithms to improve the resolution of the charge measurement. This work includes analysis and simulations of the proposed algorithms and implementation of them in an FPGA device. Besides, the tests are also conducted to evaluate the performance of the correction method. Test results indicate that the resolution of the charge measurement is successfully improved from 0.231% to 0.126% by using a signal from the shaping circuit (with the amplitude of 2 V, and leading and trailing edges of about 80 ns and 280 ns, respectively) digitized at the sampling rate of 62.5 Msps.
This paper presents the new approach in implementation of analog-to-digital converter (ADC) that is based on Hopfield neural-network architecture. Hopfield neural ADC (NADC) is a type of recurrent neural network that is effective in solving simple optimization problems, such as analog-to-digital conversion. The main idea behind the proposed design is to use multiple 2-bit Hopfield NADCs operating as quantizers in parallel, where analog input signal to each successive 2-bit Hopfield ADC block is passed through a voltage level shifter. This is followed by a neural network encoder to remove the quantization errors. In traditional Hopfield NADC based designs, increasing the number of bits could require proper scaling of the network parameters, in particular digital output operating region. Furthermore, the resolution improvement of traditional Hopfield NADC creates digital error that increases with the increasing number of bits. The proposed design is scalable in number of bits and number of quantization levels, and can maintain the magnitude of digital output code within a manageable operating voltage range.
117 - Callum Deakin , Zhixin Liu 2019
Photonic analog to digital conversion offers promise to overcome the signal-to-noise ratio (SNR) and sample rate trade-off in conventional analog to digital converters (ADCs), critical for modern digital communications and signal analysis. We propose using phase-stable dual frequency combs with a fixed frequency spacing offset to downconvert spectral slices of a broadband signal and enable high resolution parallel digitization. To prove the concept of our proposed method, we demonstrate the detection of a 10-GHz subcarrier modulated (SCM) signal using 500-MHz bandwidth ADCs by optically converting the SCM signal to ten 1-GHz bandwidth signals that can be processed in parallel for full signal detection and reconstruction. Using sinusoidal wave based standard ADC testing, we demonstrate a spurious-free dynamic range (SFDR) of >45dB and signal-to-noise-and-distortion (SINAD) of >20dB, only limited by the receiver front-end design. Our experimental investigation reveals that this SINAD limitation can be overcome by improved receiver design, promising high resolution ADC for broadband signals.
In a growing number of applications, there is a need to digitize signals whose spectral characteristics are challenging for traditional Analog-to-Digital Converters (ADCs). Examples, among others, include systems where the ADC must acquire at once a very wide but sparsely and dynamically occupied bandwidth supporting diverse services, as well as systems where the signal of interest is subject to strong narrowband co-channel interference. In such scenarios, the resolution requirements can be prohibitively high. As an alternative, the recently proposed modulo-ADC architecture can in principle require dramatically fewer bits in the conversation to obtain the target fidelity, but requires that information about the spectrum be known and explicitly taken into account by the analog and digital processing in the converter, which is frequently impractical. To address this limitation, we develop a blind version of the architecture that requires no such knowledge in the converter, without sacrificing performance. In particular, it features an automatic modulo-level adjustment and a fully adaptive modulo unwrapping mechanism, allowing it to asymptotically match the characteristics of the unknown input signal. In addition to detailed analysis, simulations demonstrate the attractive performance characteristics in representative settings.
comments
Fetching comments Fetching comments
Sign in to be able to follow your search criteria
mircosoft-partner

هل ترغب بارسال اشعارات عن اخر التحديثات في شمرا-اكاديميا