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Register a new userReadout Electronics for CEPC Semi-Digital Hadron Calorimeter Pre-prototype
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CEPC (Circular Electron and Positron Collider) is a large experiment facility proposed by Chinese particle physics community. One of its running option is being the Higgs factory. Calorimeter is the main part of this experiment to measure the jet energy. Semi-digital hadron calorimeter (SDHCAL) is one of the options for the hadron measurement. GEM detector with its high position resolution and flexible configuration is one of the candidates for the active layer of the SDHCAL. The main purpose of this paper is to provide a feasible readout method for the GEM-based semi-digital hadron calorimeter. A small-scale prototype is designed and implemented, including front-end board (FEB) and data interface board (DIF). The prototype electronics has been tested. The equivalent RMS noise of all channels is below 0.35fC. The dynamic range is up to 500fC and the gain variation is less than 1%. The readout electronics is applied on a double-layer GEM detector with 1cm*1cm readout pad. Result indicates that the electronics works well with the detector. The detection efficiency of MIP is over 95% with 5fC threshold.
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A novel hadron calorimeter is being developed for future lepton colliding beam detectors. The calorimeter is optimized for the application of Particle Flow Algorithms (PFAs) to the measurement of hadronic jets and features a very finely segmented readout with 1 x 1 cm2 cells. The active media of the calorimeter are Resistive Plate Chambers (RPCs) with a digital, i.e. one-bit, readout. To first order the energy of incident particles in this calorimeter is reconstructed as being proportional to the number of pads with a signal over a given threshold. A large-scale prototype calorimeter with approximately 500,000 readout channels has been built and underwent extensive testing in the Fermilab and CERN test beams. This paper reports on the design, construction, and commissioning of the electronic readout system of this prototype calorimeter. The system is based on the DCAL front-end chip and a VME-based back-end.
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The CALICE Semi-Digital Hadronic CALorimeter (SDHCAL) prototype using Glass Resistive Plate Chambers as a sensitive medium is the first technological prototype of a family of high-granularity calorimeters developed by the CALICE collaboration to equip the experiments of future leptonic colliders. It was exposed to beams of hadrons, electrons and muons several times in the CERN PS and SPS beamlines between 2012 and 2018. We present here a new method of particle identification within the SDHCAL using the Boosted Decision Trees (BDT) method applied to the data collected in 2015. The performance of the method is tested first with Geant4-based simulated events and then on the data collected by the SDHCAL in the energy range between 10 and 80~GeV with 10~GeV energy steps. The BDT method is then used to reject the electrons and muons that contaminate the SPS hadron beams.
In the context of developing a hadron calorimeter with extremely fine granularity for the application of Particle Flow Algorithms to the measurement of jet energies at a future lepton collider, we report on extensive tests of a small scale prototype calorimeter. The calorimeter contained up to 10 layers of Resistive Plate Chambers (RPCs) with 2560 1 times 1 cm2 readout pads, interleaved with steel absorber plates. The tests included both long-term Cosmic Ray data taking and measurements in particle beams, where the response to broadband muons and to pions and positrons with energies in the range of 1 - 16 GeV was established. Detailed measurements of the chambers efficiency as function of beam intensity have also been performed using 120 GeV protons at varying intensity. The data are compared to simulations based on GEANT4 and to analytical calculations of the rate limitations.
The BGO calorimeter, which provides a wide measurement range of the primary cosmic ray spectrum, is a key sub-detector of Dark Matter Particle Explorer (DAMPE). The readout electronics of calorimeter consists of 16 pieces of Actel ProASIC Plus FLASH-based FPGA, of which the design-level flip-flops and embedded block RAMs are single event upset (SEU) sensitive in the harsh space environment. Therefore to comply with radiation hardness assurance (RHA), SEU mitigation methods, including partial triple modular redundancy (TMR), CRC checksum, and multi-domain reset are analyzed and tested by the heavy-ion beam test. Composed of multi-level redundancy, a FPGA design with the characteristics of SEU tolerance and low resource consumption is implemented for the readout electronics.
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