Subscribe to the gold package and get unlimited access to Shamra Academy
Register a new userTesting of Front-End Readout Prototype ASICs Designed for WCDA in LHAASO
130
0
0.0
(
0
)
Ask ChatGPT about the research
No Arabic abstract
The water Cherenkov detector array (WCDA) is one of the key detectors in the large high altitude air shower observatory (LHAASO), which is proposed for very high gamma ray source survey. In WCDA, there are more than 3000 photomultiplier tubes (PMTs) scattered under water in an area of 80000 m2. As for the WCDA readout electronics, both high precision time and charge measurement is required over a large dynamic range from 1 photon electron (P.E.) to 4000 P.E. To reduce the electronics complexity and improve the system reliability, a readout scheme based on application specific integrated circuits (ASICs) is proposed. Two prototype ASICs were designed and tested. The first ASIC integrates amplification and shaping circuits for charge measurement and discrimination circuits used for time measurement. The shaped signal is further fed to the second ADC ASIC, while the output signal from the discriminator is digitized by the FPGA-based time-to-digital converter (TDC). Test results indicate that time resolution is better than 250 ps RMS, and the charge resolution is better than 10% at 1 P.E., and 1% at 4000 P.E. which meets the requirements of the LHAASO WCDA.
rate research
Read More
Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 um CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.
In the Large High Altitude Air Shower Observatory (LHAASO), the Water Cherenkov Detector Array (WCDA) is one of the key parts. The WCDA consists of 3600 Photomultiplier Tubes (PMTs) scattered in a 90000 m2 area, and both high precision time and charge measurements are required over a large dynamic range from 1 to 4000 Photo Electrons (P.E.). To achieve time measurement precision better than 500 ps RMS, high quality clock distribution and automatic phase compensation are needed among the 400 Front End Electronics (FEE) modules. To simplify the readout electronics architecture, clock, data, and commands are transferred simultaneously over 400-meter fibers, while high speed data transfer interface is implemented based on TCP/IP protocol. Design and testing of the readout electronics prototype for WCDA is presented in this paper. Test results indicate that a charge resolution better than 10% RMS @ 1 P.E. and 1% RMS @ 4000 P.E., and a time resolution better than 300 ps RMS are successfully achieved over the whole dynamic range, beyond the application requirement.
The Water Cherenkov Detector Array (WCDA) is one of the key parts in the Large High Altitude Air Shower Observatory (LHAASO). In the WCDA, 3600 Photomultiplier Tubes (PMTs) and the Front End Electronics (FEEs) are scattered within a 90000 m2 area, while a time measurement resolution better than 0.5 ns is required in the readout electronics. To achieve such time measurement precision, high quality clock distribution and synchronization among the 400 FEEs (each FEE for 9 PMTs readout) is required. To simplify the electronics system architecture, data, commands, and clock are transmitted simultaneously through fibers over a 400-meter distance between FEEs and the Clock and Data Transfer Modules (CDTMs). In this article, we propose a new method based on the White Rabbit (WR) to achieve completely automatic clock phase alignment between different FEEs. The original WR is enhanced to overcome the clock delay fluctuations due to ambient temperature variations. This paper presents the general scheme, the design of prototype electronics, and initial test results. These indicate that a clock synchronization precision better than 50 ps is achieved over 1 km fibers, which is well beyond the application requirement.
We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.
In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO), both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. for the PMT signal readout. In this paper, we present our work on the design of time discrimination circuits in LHAASO WCDA, especially on improvement to reduce the circuit dead time. Several approaches were studied through analysis and simulations, and actual circuits were designed and tested in the laboratory to evaluate the performance. Test results indicate that a time resolution better than 500 ps RMS is achieved in the whole large dynamic range, and the circuit dead time is successfully reduced to less than 200 ns.
Log in to be able to interact and post comments
comments
Fetching comments
Sign in to be able to follow your search criteria
