A new prototype of STAR inner Time Projection Chamber (iTPC) MWPC sector has been fabricated and tested in an X-ray test system. The wire chamber built at Shandong University has a wire tension precision better than 6$%$ and wire pitch precision better than 10 $mu$m. The gas gain uniformity and energy resolution are measured to be better than 1$%$ (RMS) and 20$%$ (FWHM), respectively, using an $^{55}$Fe X-ray source. The iTPC upgrade project is to replace all 24 STAR TPC inner sectors as a crucial detector upgrade for the RHIC beam energy scan phase II program. The test results show that the constructed iTPC prototype meets all project requirements.
A new pixel detector for the CMS experiment was built in order to cope with the instantaneous luminosities anticipated for the Phase~I Upgrade of the LHC. The new CMS pixel detector provides four-hit tracking with a reduced material budget as well as new cooling and powering schemes. A new front-end readout chip mitigates buffering and bandwidth limitations, and allows operation at low comparator thresholds. In this paper, comprehensive test beam studies are presented, which have been conducted to verify the design and to quantify the performance of the new detector assemblies in terms of tracking efficiency and spatial resolution. Under optimal conditions, the tracking efficiency is $99.95pm0.05,%$, while the intrinsic spatial resolutions are $4.80pm0.25,mu mathrm{m}$ and $7.99pm0.21,mu mathrm{m}$ along the $100,mu mathrm{m}$ and $150,mu mathrm{m}$ pixel pitch, respectively. The findings are compared to a detailed Monte Carlo simulation of the pixel detector and good agreement is found.
The upgrade to the High Luminosity Large Hadron Collider will pose unprecedented challenges to the tracking systems of all experiments. Recent advancement of active pixel detectors designed in CMOS processes provide attractive alternatives to the well-established hybrid design using passive sensors. This article presents studies with a high-voltage CMOS active pixel sensor designed for the ATLAS tracker upgrade. The sensor is glued to the read-out chip of the Insertable B-Layer. The device under test is structured in smaller pixels than those of the attached read-out chip with information on the hit CMOS pixel encoded in the output signal (subpixel encoding). Test beam measurements mapping recorded hits in the read-out chip to CMOS pixels, thus validating the subpixel encoding, are described.
We present the characterization and quality control test of a gigabit cable receiver ASIC prototype, GBCR2, for the ATLAS Inner Tracker pixel detector upgrade. GBCR2 equalizes and retimes the uplink electrical signals from RD53B through a 6 m Twinax AWG34 cable to lpGBT. GBCR2 also pre-emphasizes downlink command signals through the same electrical connection from lpGBT to RD53B. GBCR2 has seven uplink channels each at 1.28 Gbps and two downlink channels each at 160 Mbps. The prototype is fabricated in a 65 nm CMOS process. The characterization of GBCR2 has been demonstrated that the total jitter of the output signal is 129.1 ps (peak-peak) in the non-retiming mode or 79.3 ps (peak-peak) in the retiming mode for the uplink channel and meets the requirements of lpGBT. The total power consumption of all uplink channels is 87.0 mW in the non-retiming mode and 101.4 mW in the retiming mode, below the specification of 174 mW. The two downlink channels consume less than 53 mW. A quality control test procedure is proposed and 169 prototype chips are tested. The yield is about 97.0%.
The upgrade of the ALICE TPC will allow the experiment to cope with the high interaction rates foreseen for the forthcoming Run 3 and Run 4 at the CERN LHC. In this article, we describe the design of new readout chambers and front-end electronics, which are driven by the goals of the experiment. Gas Electron Multiplier (GEM) detectors arranged in stacks containing four GEMs each, and continuous readout electronics based on the SAMPA chip, an ALICE development, are replacing the previous elements. The construction of these new elements, together with their associated quality control procedures, is explained in detail. Finally, the readout chamber and front-end electronics cards replacement, together with the commissioning of the detector prior to installation in the experimental cavern, are presented. After a nine-year period of R&D, construction, and assembly, the upgrade of the TPC was completed in 2020.
The Inner Tracking System (ITS) of the ALICE experiment will be upgraded during the second long LHC shutdown in $mathrm{2019}-mathrm{2020}$. The main goal of the ALICE ITS Upgrade is to enable high precision measurements of low - momentum particles (< 1 GeV/c) by acquiring a large sample of events, benefiting from the increase of the LHC instantaneous luminosity of $mathrm{Pb}-mathrm{Pb}$ collisions to $mathcal{L} = 6 cdot 10^{27} cm^{-2} s^{-1} $ during Run 3. Working in this direction the ITS upgrade project is focusing on the increase of the readout rate, on the improvement of the impact parameter resolution, as well as on the improvement of the tracking efficiency and the position resolution. The major setup modification is the substitution of the current ITS with seven layers of silicon pixel detectors. The ALPIDE chip, a CMOS Monolithic Active Pixel Sensor (MAPS), was developed for this purpose and offers a spatial resolution of 5 $mu$m. The use of MAPS together with a stringent mechanical design allows for the reduction of the material budget down to 0.35% $X_0$ for the innermost layers and 1% $X_0$ for the outer layers. The detector design was validated during the research and development period through a variety of tests ensuring the proper operation for the full lifetime inside ALICE. The production phase is close to completion with all the new assembled components undergoing different tests that aim to characterize the modules and staves and determine their qualification level. This contribution describes the detector design, the measurements performed during the research and development phase, as well as the production status.