Do you want to publish a course? Click here

Memory effect in ferroelectric single electron transistor: violation of conductance periodicity in the gate voltage

181   0   0.0 ( 0 )
 Publication date 2014
  fields Physics
and research's language is English




Ask ChatGPT about the research

The fundamental property of most single-electron devices with quasicontinuous quasiparticle spectrum on the island is the periodicity of their transport characteristics in the gate voltage. This property is robust even with respect to placing the ferroelectric insulators in the source and drain tunnel junctions. We show that placing the ferroelectric inside the gate capacitance breaks this periodicity. The current-voltage characteristics of this SET strongly depends on the ferroelectric polarization and shows the giant memory-effect even for negligible ferroelectric hysteresis making this device promising for memory applications.



rate research

Read More

Single dopants in semiconductor nanostructures have been studied in great details recently as they are good candidates for quantum bits, provided they are coupled to a detector. Here we report coupling of a single As donor atom to a single-electron transistor (SET) in a silicon nanowire field-effect transistor. Both capacitive and tunnel coupling are achieved, the latter resulting in a dramatic increase of the conductance through the SET, by up to one order of magnitude. The experimental results are well explained by the rate equations theory developed in parallel with the experiment.
We report on combined measurements of heat and charge transport through a single-electron transistor. The device acts as a heat switch actuated by the voltage applied on the gate. The Wiedemann-Franz law for the ratio of heat and charge conductances is found to be systematically violated away from the charge degeneracy points. The observed deviation agrees well with the theoretical expectation. With large temperature drop between the source and drain, the heat current away from degeneracy deviates from the standard quadratic dependence in the two temperatures.
Using a time-dependent Anderson Hamiltonian, a quantum dot with an ac voltage applied to a nearby gate is investigated. A rich dependence of the linear response conductance on the external frequency and driving amplitude is demonstrated. At low frequencies the ac potential produces sidebands of the Kondo peak in the spectral density of the dot, resulting in a logarithmic decrease in conductance over several decades of frequency. At intermediate frequencies, the conductance of the dot displays an oscillatory behavior due to the appearance of Kondo resonances of the satellites of the dot level. At high frequencies, the conductance of the dot can vary rapidly due to the interplay between photon-assisted tunneling and the Kondo resonance.
We propose and analyze a novel dual-gate Spin Field Effect Transistor (SpinFET) with half-metallic ferromagnetic source and drain contacts. The transistor has two gate pads that can be biased independently. It can be switched ON or OFF with a few mV change in the differential bias between the two pads, resulting in extremely low dynamic power dissipation during switching. The ratio of ON to OFF conductance remains fairly large (~ 60) up to a temperature of 10 K. This device also has excellent inverter characteristics, making it attractive for applications in low power and high density Boolean logic circuits.
Silicon ferroelectric field-effect transistors (FeFETs) with low-k interfacial layer (IL) between ferroelectric gate stack and silicon channel suffers from high write voltage, limited write endurance and large read-after-write latency due to early IL breakdown and charge trapping and detrapping at the interface. We demonstrate low voltage, high speed memory operation with high write endurance using an IL-free back-end-of-line (BEOL) compatible FeFET. We fabricate IL-free FeFETs with 28nm channel length and 126nm width under a thermal budget <400C by integrating 5nm thick Hf0.5Zr0.5O2 gate stack with amorphous Indium Tungsten Oxide (IWO) semiconductor channel. We report 1.2V memory window and read current window of 10^5 for program and erase, write latency of 20ns with +/-2V write pulses, read-after-write latency <200ns, write endurance cycles exceeding 5x10^10 and 2-bit/cell programming capability. Array-level analysis establishes IL-free BEOL FeFET as a promising candidate for logic-compatible high-performance on-chip buffer memory and multi-bit weight cell for compute-in-memory accelerators.
comments
Fetching comments Fetching comments
mircosoft-partner

هل ترغب بارسال اشعارات عن اخر التحديثات في شمرا-اكاديميا