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Register a new userDevelopment of COTS ADC SEE Test System for the ATLAS LAr Calorimeter Upgrade
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Radiation-tolerant, high speed, high density and low power commercial off-the-shelf (COTS) analog-to-digital converters (ADCs) are planned to be used in the upgrade to the Liquid Argon (LAr) calorimeter front end (FE) trigger readout electronics. Total ionization dose (TID) and single event effect (SEE) are two important radiation effects which need to be characterized on COTS ADCs. In our initial TID test, Texas Instruments (TI) ADS5272 was identified to be the top performer after screening a total 17 COTS ADCs from different manufacturers with dynamic range and sampling rate meeting the requirements of the FE electronics. Another interesting feature of ADS5272 is its 6.5 clock cycles latency, which is the shortest among the 17 candidates. Based on the TID performance, we have designed a SEE evaluation system for ADS5272, which allows us to further assess its radiation tolerance. In this paper, we present a detailed design of ADS5272 SEE evaluation system and show the effectiveness of this system while evaluating ADS5272 SEE characteristics in multiple irradiation tests. According to TID and SEE test results, ADS5272 was chosen to be implemented in the full-size LAr Trigger Digitizer Board (LTDB) demonstrator, which will be installed on ATLAS calorimeter during the 2014 Long Shutdown 1 (LS1).
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Short Baseline Near Detector (SBND), which is a 260-ton LAr TPC as near detector in Short Baseline Neutrino (SBN) program, consists of 11,264 TPC readout channels. As an enabling technology for noble liquid detectors in neutrino experiments, cold electronics developed for extremely low temperature (77K - 89K) decouples the electrode and cryostat design from the readout design. With front-end electronics integrated with detector electrodes, the noise is independent of the fiducial volume and about half as with electronics at room temperature. Digitization and signal multiplexing to high speed serial links inside cryostat result in large reduction in the quantity of cables (less outgassing) and the number of feed-throughs, therefore minimize the penetration and simplify the cryostat design. Being considered as an option for the TPC readout, several Commercial-Off-The-Shelf (COTS) ADC chips have been identified as good candidates for operation in cryogenic temperature after initial screening test. Because Hot Carrier Effects (HCE) degrades CMOS device lifetime, one candidate, ADI AD7274 fabricated in TSMC 350nm CMOS technology, of which lifetime at cryogenic temperature is studied. The lifetime study includes two phases, the exploratory phase and the validation phase. This paper describes the test method, test setup, observations in the exploratory phase and the validation phase. Based on the current test data, the preliminary lifetime projection of AD7274 is about 6.1 $times$ $10^6$ years at 2.5V operation at cryogenic temperature, which means the HCE degradation is negligible during the SBND service life.
A completely New Small Wheel (NSW) will be constructed for ATLAS Phase-1 upgrade. Small-Strip Thin-Gap-Chamber (sTGC) will devote to the trigger function of NSW. A full-size sTGC quadruplet consists of 4 layers, and will need 4 pad Front-End-Boards and 4 strip Front-End-Boards for sTGC signals readout. The 8 boards should be readout simultaneously at a time. This paper presents the study of multi-layer sTGC test system, a FEB Driver Card (FEBDC) is designed for pFEB and sFEB boards handling. The design and test of FEBDC are described in details.
The FEB(front end board) configuration test board is developed aiming at meeting the requirement of testing the new generation ASIC(application-specific integrated circuit) chips and its configuration system for ATLAS NSW(New Small Wheel) upgrade, In this paper, some functions are developed in terms of the configurations of the key chips on the FEB, VMM3 and TDS2 using GBT-SCA. Additionally, a flexible communication protocol is designed, verifying the whole data link. It provides technical reference for prototype FEB key chip configuration and data readout, as well as the final system configuration.
A Liquid-argon Trigger Digitizer Board (LTDB) is being developed to upgrade the ATLAS Liquid Argon Calorimeter Phase-I trigger electronics. The LTDB located at the front end needs to obtain the clock signals and be configured and monitored remotely from the back end. A clock and control system is being developed for the LTDB and the major functions of the system have been evaluated. The design and evaluation of the clock and control system are presented in this paper.
Following the Higgs particle discovery, the Large Hadron Collider complex will be upgraded in several phases allowing the luminosity to increase to $7 times 10^{34}cm^{-2}s^{-1}$. In order to adapt the ATLAS detector to the higher luminosity environment after the upgrade, part of the ATLAS muon end-cap system, the Small Wheel, will be replaced by the New Small Wheel. The New Small Wheel includes two kinds of detectors: small-strip Thin Gap Chambers and Micromegas. Shandong University, part of the ATLAS collaboration, participates in the construction of the ATLAS New Small Wheel by developing, producing and testing the performance of part of the small-strip Thin Gap Chambers. This paper describes the construction and cosmic-ray testing of small-strip Thin Gap Chambers in Shandong University.
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