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Register a new userCharacterization of InSb quantum wells with atomic layer deposited gate dielectrics
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We report magnetotransport measurements of a gated InSb quantum well (QW) with high quality Al2O3 dielectrics (40 nm thick) grown by atomic layer deposition. The magnetoresistance data demonstrate a parallel conduction channel in the sample at zero gate voltage (Vg). A good interface between Al2O3 and the top InSb layer ensures that the parallel channel is depleted at negative Vg and the density of two-dimensional electrons in the QW is tuned by Vg with a large ratio of 6.5x1014 m-2V-1 but saturates at large negative Vg. These findings are closely related to layer structures of the QW as suggested by self-consistent Schrodinger-Poisson simulation and two-carrier model.
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Carbon nanotube field-effect transistors (CNT FETs) have been proposed as possible building blocks for future nano-electronics. But a challenge with CNT FETs is that they appear to randomly display varying amounts of hysteresis in their transfer characteristics. The hysteresis is often attributed to charge trapping in the dielectric layer between the nanotube and the gate. This study includes 94 CNT FET samples, providing an unprecedented basis for statistics on the hysteresis seen in five different CNT-gate configurations. We find that the memory effect can be controlled by carefully designing the gate dielectric in nm-thin layers. By using atomic layer depositions (ALD) of HfO$_{2}$ and TiO$_{2}$ in a triple-layer configuration, we achieve the first CNT FETs with consistent and narrowly distributed memory effects in their transfer characteristics.
We investigated the gate control of a two-dimensional electron gas (2DEG) confined to InSb quantum wells with an Al2O3 gate dielectric formed by atomic layer deposition on a surface layer of Al0.1In0.9Sb or InSb. The wider bandgap of Al0.1In0.9Sb compared to InSb resulted in a linear, sharp, and non-hysteretic response of the 2DEG density to gate bias in the structure with an Al0.1In0.9Sb surface layer. In contrast, a nonlinear, slow, and hysteretic (nonvolatile-memory-like) response was observed in the structure with an InSb surface layer. The 2DEG with the Al0.1In0.9Sb surface layer was completely depleted by application of a small gate voltage (-0.9 V).
We analyze the effect of screening provided by the additional graphene layer in double layer graphene heterostructures (DLGs) on transport characteristics of DLG devices in the metallic regime. The effect of gate-tunable charge density in the additional layer is two-fold: it provides screening of the long-range potential of charged defects in the system, and screens out Coulomb interactions between charge carriers. We find that the efficiency of defect charge screening is strongly dependent on the concentration and location of defects within the DLG. In particular, only a moderate suppression of electron-hole puddles around the Dirac point induced by the high concentration of remote impurities in the silicon oxide substrate could be achieved. A stronger effect is found on the elastic relaxation rate due to charged defects resulting in mobility strongly dependent on the electron denisty in the additional layer of DLG. We find that the quantum interference correction to the resistivity of graphene is also strongly affected by screening in DLG. In particular, the dephasing rate is strongly suppressed by the additional screening that supresses the amplitude of electron-electron interaction and reduces the diffusion time that electrons spend in proximity of each other. The latter effect combined with screening of elastic relaxation rates results in a peculiar gate tunable weak-localization magnetoresistance and quantum correction to resistivity. We propose suitable experiments to test our theory and discuss the possible relevance of our results to exisiting data.
Metal-oxide-semiconductor field-effect transistors (MOSFETs) using atomic-layer-deposited (ALD) Al$_2$O$_3$ as the gate dielectric are fabricated on the Si/Si$_{1-x}$Ge$_x$ heterostructures. The low-temperature carrier density of a two-dimensional electron system (2DES) in the strained Si quantum well can be controllably tuned from 2.5$times10^{11}$cm$^{-2}$ to 4.5$times10^{11}$cm$^{-2}$, virtually without any gate leakage current. Magnetotransport data show the homogeneous depletion of 2DES under gate biases. The characteristic of vertical modulation using ALD dielectric is shown to be better than that using Schottky barrier or the SiO$_2$ dielectric formed by plasma-enhanced chemical-vapor-deposition(PECVD).
Gate-tunable high-mobility InSb/In_{1-x}Al_{x}Sb quantum wells (QWs) grown on GaAs substrates are reported. The QW two-dimensional electron gas (2DEG) channel mobility in excess of 200,000 cm^{2}/Vs is measured at T=1.8K. In asymmetrically remote-doped samples with an HfO_{2} gate dielectric formed by atomic layer deposition, parallel conduction is eliminated and complete 2DEG channel depletion is reached with minimal hysteresis in gate bias response of the 2DEG electron density. The integer quantum Hall effect with Landau level filling factor down to 1 is observed. A high-transparency non-alloyed Ohmic contact to the 2DEG with contact resistance below 1{Omega} cdot mm is achieved at 1.8K.
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