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Register a new userRNA interference and Register Machines (extended abstract)
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Publication date
2012
fields
Informatics Engineering
and research's language is
English
Authors
Masahiro Hamano
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RNA interference (RNAi) is a mechanism whereby small RNAs (siRNAs) directly control gene expression without assistance from proteins. This mechanism consists of interactions between RNAs and small RNAs both of which may be single or double stranded. The target of the mechanism is mRNA to be degraded or aberrated, while the initiator is double stranded RNA (dsRNA) to be cleaved into siRNAs. Observing the digital nature of RNAi, we represent RNAi as a Minsky register machine such that (i) The two registers hold single and double stranded RNAs respectively, and (ii) Machines instructions are interpreted by interactions of enzyme (Dicer), siRNA (with RISC com- plex) and polymerization (RdRp) to the appropriate registers. Interpreting RNAi as a computational structure, we can investigate the computational meaning of RNAi, especially its complexity. Initially, the machine is configured as a Chemical Ground Form (CGF), which generates incorrect jumps. To remedy this problem, the system is remodeled as recursive RNAi, in which siRNA targets not only mRNA but also the machine instructional analogues of Dicer and RISC. Finally, probabilistic termination is investigated in the recursive RNAi system.
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An abstract machine is a theoretical model designed to perform a rigorous study of computation. Such a model usually consists of configurations, instructions, programs, inputs and outputs for the machine. In this paper we formalize these notions as a very simple algebraic system, called a configuration machine. If an abstract machine is defined as a configuration machine consisting of primitive recursive functions then the functions computed by the machine are always recursive. The theory of configuration machines provides a useful tool to study universal machines.
Process behaviour is often defined either in terms of the tests they satisfy, or in terms of the logical properties they enjoy. Here we compare these two approaches, using extensional testing in the style of DeNicola, Hennessy, and a recursive version of the property logic HML. We first characterise subsets of this property logic which can be captured by tests. Then we show that those subsets of the property logic capture precisely the power of tests.
This is an extended abstract presenting new results on the topological complexity of omega-powers (which are included in a paper Classical and effective descriptive complexities of omega-powers available from arXiv:0708.4176) and reflecting also some open questions which were discussed during the Dagstuhl seminar on Topological and Game-Theoretic Aspects of Infinite Computations 29.06.08 - 04.07.08.
We introduce a notion of real-valued reward testing for probabilistic processes by extending the traditional nonnegative-reward testing with negative rewards. In this richer testing framework, the may and must preorders turn out to be inverses. We show that for convergent processes with finitely many states and transitions, but not in the presence of divergence, the real-reward must-testing preorder coincides with the nonnegative-reward must-testing preorder. To prove this coincidence we characterise the usual resolution-based testing in terms of the weak transitions of processes, without having to involve policies, adversaries, schedulers, resolutions, or similar structures that are external to the process under investigation. This requires establishing the continuity of our function for calculating testing outcomes.
This extended abstract reports on current progress of SMTCoq, a communication tool between the Coq proof assistant and external SAT and SMT solvers. Based on a checker for generic first-order certificates implemented and proved correct in Coq, SMTCoq offers facilities both to check external SAT and SMT answers and to improve Coqs automation using such solvers, in a safe way. Currently supporting the SAT solver zChaff, and the SMT solver veriT for the combination of the theories of congruence closure and linear integer arithmetic, SMTCoq is meant to be extendable with a reasonable amount of effort: we present work in progress to support the SMT solver CVC4 and the theory of bit vectors.
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