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Register a new userImplanted Bottom Gate for Epitaxial Graphene on Silicon Carbide
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We present a technique to tune the charge density of epitaxial graphene via an electrostatic gate that is buried in the silicon carbide substrate. The result is a device in which graphene remains accessible for further manipulation or investigation. Via nitrogen or phosphor implantation into a silicon carbide wafer and subsequent graphene growth, devices can routinely be fabricated using standard semiconductor technology. We have optimized samples for room temperature as well as for cryogenic temperature operation. Depending on implantation dose and temperature we operate in two gating regimes. In the first, the gating mechanism is similar to a MOSFET, the second is based on a tuned space charge region of the silicon carbide semiconductor. We present a detailed model that describes the two gating regimes and the transition in between.
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The materials science of graphene grown epitaxially on the hexagonal basal planes of SiC crystals is reviewed. We show that the growth of epitaxial graphene on Si-terminated SiC(0001) is much different than growth on the C-terminated SiC(000 -1) surface, and discuss the physical structure of these graphenes. The unique electronic structure and transport properties of each type of epitaxial graphene is described, as well as progress toward the development of epitaxial graphene devices. This materials system is rich in subtleties, and graphene grown on the two polar faces differs in important ways, but all of the salient features of ideal graphene are found in these epitaxial graphenes, and wafer-scale fabrication of multi-GHz devices already has been achieved.
This article presents a review of epitaxial graphene on silicon carbide, from fabrication to properties, put in the context of other forms of graphene.
We use ultra-high vacuum chemical vapor deposition to grow polycrystalline silicon carbide (SiC) on c-plane sapphire wafers which are then annealed between 1250 and 1450{deg}C in vacuum to create epitaxial multilayer graphene (MLG). Despite the surface roughness and small domain size of the polycrystalline SiC, a conformal MLG film is formed. By planarizing the SiC prior to graphene growth, a reduction of the Raman defect band is observed in the final MLG. The graphene formed on polished SiC films also demonstrates significantly more ordered layer-by-layer growth and increased carrier mobility for the same carrier density as the non-polished samples.
Realizing high-performance nanoelectronics requires control of materials at the nanoscale. Methods to produce high quality epitaxial graphene (EG) nanostructures on silicon carbide are known. The next step is to grow Van der Waals semiconductors on top of EG nanostructures. Hexagonal boron nitride (h-BN) is a wide bandgap semiconductor with a honeycomb lattice structure that matches that of graphene, making it ideally suited for graphene-based nanoelectronics. Here, we describe the preparation and characterization of multilayer h-BN grown epitaxially on EG using a migration-enhanced metalorganic vapor phase epitaxy process. As a result of the lateral epitaxial deposition (LED) mechanism, the grown h-BN/EG heterostructures have highly ordered epitaxial interfaces, as desired in order to preserve the transport properties of pristine graphene. Atomic scale structural and energetic details of the observed row-by-row, growth mechanism of the 2D epitaxial h-BN film are analyzed through first-principles simulations, demonstrating one-dimensional nucleation-free-energy-barrierless growth. This industrially relevant LED process can be applied to a wide variety of van der Waals materials.
Graphene on silicon carbide (SiC) bears great potential for future graphene electronic applications because it is available on the wafer-scale and its properties can be custom-tailored by inserting various atoms into the graphene/SiC interface. It remains unclear, however, how atoms can cross the impermeable graphene layer during this widely used intercalation process. Here we demonstrate that, in contrast to the current consensus, graphene layers on SiC are not homogeneous, but instead composed of domains of different crystallographic stacking. We show that these domains are intrinsically formed during growth and that dislocations between domains dominate the (de)intercalation dynamics. Tailoring these dislocation networks, e.g. through substrate engineering, will increase the control over the intercalation process and could open a playground for topological and correlated electron phenomena in two-dimensional superstructures.
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