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Early generations of superconducting quantum annealing processors have provided a valuable platform for studying the performance of a scalable quantum computing technology. These studies have directly informed our approach to the design of the next-generation processor. Our design priorities for this generation include an increase in per-qubit connectivity, a problem Hamiltonian energy scale similar to previous generations, reduced Hamiltonian specification errors, and an increase in the processor scale that also leaves programming and readout times fixed or reduced. Here we discuss the specific innovations that resulted in a processor architecture that satisfies these design priorities.
We have developed a quantum annealing processor, based on an array of tunably coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process [1]. Implementing this type of processor at a scale of 512 qubits and 1472 programm
Entanglement lies at the core of quantum algorithms designed to solve problems that are intractable by classical approaches. One such algorithm, quantum annealing (QA), provides a promising path to a practical quantum processor. We have built a serie
More computational resources (i.e., more physical qubits and qubit connections) on a superconducting quantum processor not only improve the performance but also result in more complex chip architecture with lower yield rate. Optimizing both of them s
As progress is made towards the first generation of error-corrected quantum computers, careful characterization of a processors noise environment will be crucial to designing tailored, low-overhead error correction protocols. While standard coherence
The required precision to perform quantum simulations beyond the capabilities of classical computers imposes major experimental and theoretical challenges. Here, we develop a characterization technique to benchmark the implementation precision of a s