ﻻ يوجد ملخص باللغة العربية
We theoretically consider a cross-resonance (CR) gate implemented by pulse sequences proposed by Calderon-Vargas & Kestner, Phys. Rev. Lett. 118, 150502 (2017). These sequences mitigate systematic error to first order, but their effectiveness is limited by one-qubit gate imperfections. Using additional microwave control pulses, it is possible to tune the effective CR Hamiltonian into a regime where these sequences operate optimally. This improves the overall feasibility of these sequences by reducing the one-qubit operations required for error correction. We illustrate this by simulating randomized benchmarking for a system of weakly coupled transmons and show that while this novel pulse sequence does not offer an advantage with the current state of the art in transmons, it does improve the scaling of CR gate infidelity with one-qubit gate infidelity.
We present a comprehensive theoretical study of the cross-resonance gate operation covering estimates for gate parameters and gate error as well as analyzing spectator qubits and multi-qubit frequency collisions. We start by revisiting the derivation
Building upon the demonstration of coherent control and single-shot readout of the electron and nuclear spins of individual 31-P atoms in silicon, we present here a systematic experimental estimate of quantum gate fidelities using randomized benchmar
Off-resonant error for a driven quantum system refers to interactions due to the input drives having non-zero spectral overlap with unwanted system transitions. For the cross-resonance gate, this includes leakage as well as off-diagonal computational
Implementation of high-fidelity swapping operations is of vital importance to execute quantum algorithms on a quantum processor with limited connectivity. We present an efficient pulse control technique, cross-cross resonance (CCR) gate, to implement
The control and handling of errors arising from cross-talk and unwanted interactions in multi-qubit systems is an important issue in quantum information processing architectures. We introduce a benchmarking protocol that provides information about th