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تسجيل مستخدم جديدFPGA-based Time to Digital Converter and Data Acquisition system for High Energy Tagger of KLOE-2 experiment
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In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.
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Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of off-the-shelf TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable G
ate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition systems and the interface to the online FARM of KLOE-2.
The KLOE experiment at the upgraded DAFNE e+e- collider in Frascati (KLOE-2) is going to start a new data taking at the beginning of 2010 with its detector upgraded with a tagging system for the identification of gamma-gamma interactions. The tagging
stations for low-energy e+e- will consist in two calorimeters The calorimeter used to detect low-energy e+e- will be placed between the beam-pipe outer support structure and the inner wall of the KLOE drift chamber. This calorimeter will be made of LYSO crystals readout by Silicon Photomultipliers, to achieve an energy resolution better than 8% at 200 MeV.
In order to fully reconstruct to the reaction e+e- to e+e- gamma-gamma in the energy region of the phi meson production, new detectors along the DAFNE beam line have to be installed in order to detect the scattered e+e-. The High Energy Tagger (HET)
detector measures the deviation of leptons from their main orbit by determining their position and timing so to tag gamma-gamma physics events and disentangle them from background. The HET detectors are placed at the exit of the DAFNE dipole magnets, 11 m away from the IP, both on positron and electron lines. The HET sensitive area is made up of a set of 28 plastic scintillators. A dedicated DAQ electronics board based on a Xilinx Virtex-5 FPGA have been developed for this detector. It provides a MultiHit TDC with a time resolution of the order of 500 ps and the possibility to acquire data any 2.5 ns, thus allowing to clearly identify the correct bunch crossing. First results of the commissioning run are presented.
Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope wi
th the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.
The JSNS$^{2}$ (J-PARC Sterile Neutrino Search at J-PARC Spallation Neutron Source) experiment aims to search for neutrino oscillations over a 24 m short baseline at J-PARC. The JSNS$^{2}$ inner detector is filled with 17 tons of gadolinium(Gd)-loade
d liquid scintillator (LS) with an additional 31 tons of unloaded LS in the intermediate $gamma$-catcher and an optically separated outer veto volumes. A total of 120 10-inch photomultiplier tubes observe the scintillating optical photons and each analog waveform is stored with the flash analog-to-digital converters. We present details of the data acquisition, processing, and data quality monitoring system. We also present two different trigger logics which are developed for the beam and self-trigger.
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