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تسجيل مستخدم جديدPARISROC, a photomultiplier array readout chip
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PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology, for photomultipliers array. It is a front-end electronics ASIC which allows triggerless acquisition for the next generation of neutrino experiments. These detectors have place in megaton size water tanks and will require very large surface of photo-detection. An R & D program, funded by French national agency for research and called PMm2, proposes to segment the very large surface of photo-detection in macro pixels made of 16 photomultiplier tubes connected to an autonomous front-end electronics. The ASIC allows triggerless acquisition and only send out the relevant data by network to the central data storage. This data management reduces considerably the cost of these detectors. This paper describes the front-end electronics ASIC called PARISROC which integrates totally independents 16 channels with a variable gain and provides charge and time measurement with a 12-bit ADC and a 24-bits Counter.
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PARISROC is a complete read out chip, in AMS SiGe 0.35 micron technology [1], for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency
for research (ANR) called PMm2: Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles [2] (ref.ANR-06-BLAN- 0186). The ASIC integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo-electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.
PARISROC is a complete read out chip, in AMS SiGe 0.35 !m technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for res
earch (ANR) called PMm2: ?Innovative electronics for photodetectors array used in High Energy Physics and Astroparticles? (ref.ANR-06-BLAN-0186). The ASIC (Application Specific Integrated Circuit) integrates 16 independent and auto triggered channels with variable gain and provides charge and time measurement by a Wilkinson ADC (Analog to Digital Converter) and a 24-bit Counter. The charge measurement should be performed from 1 up to 300 photo- electrons (p.e.) with a good linearity. The time measurement allowed to a coarse time with a 24-bit counter at 10 MHz and a fine time on a 100ns ramp to achieve a resolution of 1 ns. The ASIC sends out only the relevant data through network cables to the central data storage. This paper describes the front-end electronics ASIC called PARISROC.
The performance of scintillator counters with embedded wavelength-shifting fibers has been measured in the Fermilab Meson Test Beam Facility using 120 GeV protons. The counters were extruded with a titanium dioxide surface coating and two channels fo
r fibers at the Fermilab NICADD facility. Each fiber end is read out by a 2*2 mm^2 silicon photomultiplier. The signals were amplified and digitized by a custom-made front-end electronics board. Combinations of 5*2 cm^2 and 6*2 cm^2 extrusion profiles with 1.4 and 1.8 mm diameter fibers were tested. The design is intended for the cosmic-ray veto detector for the Mu2e experiment at Fermilab. The light yield as a function of the transverse and longitudinal position of the beam will be given.
Calorimetry at future linear colliders could be based on a particle flow approach where granularity is the key to high jet energy resolution. Among different technologies, Micromegas chambers with 1 cm2 pad segmentation are studied for the active med
ium of a hadronic calorimeter. A chamber of 1 m2 with 9216 channels read out by a low noise front-end ASIC called MICROROC has recently been constructed and tested. Chamber design, ASIC circuitry and preliminary test beam results are reported.
With the ultimate goal of developing a pixel-based readout for a TPC at the ILC, a GridPix readout system consisting of one Timepix3 chip with an integrated amplification grid was embedded in a prototype detector. The performance was studied in a tes
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